A serializer-deserializer (SerDes, or SERDES) is a pair of functional blocks used for high-speed communication between two systems, such as two application-specific integrated circuits (ASICs), across a limited input/output link between the two systems.
Generally, each system will include at least one SerDes transmitter and at least one SerDes receiver, thereby allowing bidirectional communication, although some such SerDes will use only transmitters on the first system and only receivers on the second system. In any case, SerDes links are traditionally designed with standalone transmitter (TX) and receiver (RX) sides.
For a SerDes link to operate most efficiently, it is desirable for the TX and RX ends of the link to be able to share performance-related information. However, most SerDes systems do not have an inherent ability to communicate this information between the transmitter and receiver or vice-versa. SerDes links communicate high-speed data from chip to chip, but are not able to add overhead data to live bit streams, so the performance-related information cannot be encoded in the data stream. Therefore, it is not possible to communicate performance-related information when the data link is active.
One known solution to this problem is to use dedicated circuitry, pins and physical wire connections to create a backchannel for communication of performance-related information or other metadata between the TX and RX sides of the SerDes. However, this is a large, undesirable overhead since the number of pins available is tightly constrained. A block diagram of an example implementation of such a physical backchannel is shown in FIG. 1. A SerDes 100 forms a portion of a first application-specific integrated circuit (ASIC) 102 and a second ASIC 104. The SerDes 100 includes a transmitter macro 106 and a receiver macro 108. A data channel 110 allows the transmitter 106 to transmit data to the receiver 108. Physical backchannels 112 are created using physical hardware, such as pins and wires of a data connection. These backchannels 112 may be unidirectional or bidirectional, depending on the physical hardware set aside for them.
The data link may also be used to communicate performance information or other metadata, but not during operation. Existing standards and implementations use existing channels to pass data between chips at startup time as part of a hand-shaking procedure. This hand-shaking usually consists of two parts: auto negotiation (AN) and link training (LT). Auto negotiation is used mainly to configure both sides (TX and RX) to use the same standard, duplex mode and data rate. Link training is used mainly to configure TX amplitudes and equalizer settings. This communication typically happens at lower speed and requires that high speed pseudo-random bit sequence (PRBS) be transmitted periodically so that clock and data recovery (CDR) remains phase-locked.
Since this all occurs only at start up, it cannot respond to any changes in conditions during operation. Links must therefore be set pessimistically, which hurts efficiency. This also affects the speed at which links can be turned on, which further hurts efficiency.
Some techniques have been developed to embed analog back-channel communication on existing data lines.
For example, changing the common mode level of the differential TX or RX circuits may allow some metadata to be embedded in the data signal while the link is operational. One such technique is disclosed by A. Ho, et al., “Common-Mode Backchannel Signaling System for Differential High-Speed Links”, IEEE Symp. VLSI Circuits, June 2004. FIG. 2 shows an example implementation of such a technique from that publication.
However, it is difficult for this kind of modulation technique to have no impact on the signal integrity of the data, especially at very high data rates. It also requires a differential (two-wire) electrical physical link—it is not suitable for optical links or single-ended (one-wire) electrical links.
Another similar modulation technique is disclosed by P. Ta, et al., “Using Frequency Divisional Multiplexing for a high-Speed Serializer/Deserializer with Back Channel Communication”, U.S. Patent Application Number 20110038386, Published Feb. 17, 2011. SerDes links are sometimes alternating current (AC) coupled—where they are, the low-frequency part of the spectrum may be used for back-channel communication.
FIG. 3 shows an example implementation of such a technique from that publication. A circuit is shown having a first SerDes and second SerDes. The first SerDes has a forward channel driver as well as a receiver for reverse channel communication; the second SerDes has a reverse channel driver and a receiver for forward channel communication. Two AC coupling capacitors enable the circuit to utilize frequency division multiplexing, which enables bi-directional transmission across a communications medium. The forward channel passes relatively high frequency signals output by the forward channel driver through a first AC coupling capacitor, which are transmitted through the communications medium and passed through a second AC coupling capacitor to be received by the forward channel receiver. On the reverse channel, the reverse channel driver passes relatively low frequency signals, which bypass the second AC coupling capacitor through DC coupling, are transmitted through the communications medium, bypass the first AC coupling capacitor, and are received by the reverse channel receiver through DC coupling.
However, this technique is not applicable to links that are not AC coupled. It requires additional pins and external capacitors in order to set the low-frequency cutoff correctly. It also adds complexity to the analog data path, which may introduce noise or other non-idealities. As with the common mode modulation technique disclosed by Ho et al., it requires an electrical physical link and so is not suitable for optical links.